The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. The performance of a chip design is seriously influenced by the control of resistance/capacitance (RC), timing, leakage, and topology of the metal/dielectric inter-layers. Those are further related to resolution of the lithography patterning and the imaging accuracy.
To enhance the imaging effect when a design pattern is transferred to a wafer, an optical proximity correction (OPC) to minimize the proximity effect is indispensable. The design pattern is adjusted to generate an image on the wafer with improved resolution.
However, along with the progress of the lithography patterning, some other imaging effect are unavoidable and those imaging factors are location related. Those other imaging factors are not fully considered and not effectively corrected or efficiently corrected. For N28 nodes and below, the severity of main feature distortion caused by those imaging effect generates many side effects with significant impact, which is unacceptable in term of device performance, quality and reliability.
Therefore, what is needed is a method for IC design and mask making to effectively and efficiently tuning IC pattern to address the above issue.